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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4517B LSI Dual 64-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Dual 64-bit static shift register DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D input is entered into the first bit on the LOW to HIGH transition of the clock, regardless of the state of PE/EO. HEF4517B LSI When PE/EO is LOW the outputs are enabled and the device is in the 64-bit serial mode. When PE/EO is HIGH the outputs are disabled (high impedance OFF-state), the 64-bit shift register is divided into four 16-bit shift registers with D, O16, O32 and O48 as data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category LSI See Family Specifications January 1995 2 Philips Semiconductors Product specification Dual 64-bit static shift register HEF4517B LSI Fig.2 Pinning diagram. HEF4517BP(N): HEF4517BD(F): HEF4517BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING CPA, CPB PE/EOA, PE/EOB DA, DB O16A, O32A, O48A O16B, O32B, O48B O64A, O64B clock inputs parallel input-enable/output-enable inputs data inputs 3-state outputs/inputs 3-state outputs/inputs 3-state outputs January 1995 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 4 Product specification Fig.3 Logic diagram (one shift register). Philips Semiconductors Dual 64-bit static shift register HEF4517B LSI This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 5 Philips Semiconductors FUNCTION TABLE Dual 64-bit static shift register INPUTS CP D data entered into 1st bit PE/EO L O16 content of 16th bit displayed data at O16 entered into 17th bit no change Z INPUTS/OUTPUTS MODE O32 content of 32nd bit displayed data at O32 entered into 33rd bit no change Z O48 content of 48th bit displayed data at O48 entered into 49th bit no change Z O64 content of 64th bit displayed remains in `Z' state One 64-bit shift register. The content of the shift register is shifted over one stage Four 16-bit shift register. The content of the shift registers is shifted over one stage. no change no change data entered into 1st bit H X X Notes L H no change Z 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial Z = high impedance state = positive-going transition = negative-going transition Product specification HEF4517B LSI Philips Semiconductors Product specification Dual 64-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 7 000 fi + (foCL) x VDD2 28 000 fi + (foCL) x VDD2 70 000 fi + (foCL) x VDD2 where HEF4517B LSI fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL 60 30 20 60 30 20 120 60 40 120 60 40 ns ns ns ns ns ns 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 15 tPLH tPHL 220 85 60 190 75 50 440 170 120 380 150 100 ns ns ns ns ns ns 193 ns + (0,55 ns/pF) CL 74 ns + (0,23 ns/pF) CL 52 ns + (0,16 ns/pF) CL 163 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 6 Philips Semiconductors Product specification Dual 64-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Minimum clock pulse width; LOW Set-up times On, D CP Hold time On, D CP 3-state propagation delays Output disable times PE/EO On HIGH 5 10 15 5 LOW Output enable times PE/EO On HIGH 5 10 15 5 LOW Maximum clock pulse frequency 10 15 5 10 15 fmax 2 6 8 tPZL tPZH 45 25 20 60 30 25 5 12 16 90 50 40 120 60 50 ns ns ns ns ns ns MHz MHz MHz 10 15 tPLZ tPHZ 40 30 25 50 30 25 80 60 50 100 60 50 ns ns ns ns ns ns 5 10 15 5 10 15 5 10 15 thold tsu 30 25 20 45 30 25 tWCPL SYMBOL MIN. TYP. 95 40 30 10 5 5 15 10 10 MAX. 190 80 60 ns ns ns ns ns ns ns ns ns HEF4517B LSI see also waveforms Fig.4. January 1995 7 Philips Semiconductors Product specification Dual 64-bit static shift register HEF4517B LSI Fig.4 Waveforms showing minimum clock pulse width, set-up and hold times for On (as data input) and D to CP. January 1995 8 |
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